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| LSI/CSI UL (R) LS7060/7062 (631) 271-0400 FAX (631) 271-0405 LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 A3800 32 BIT/DUAL 16 BIT BINARY UP COUNTER WITH BYTE MULTIPLEXED THREE-STATE OUTPUTS FEATURES: * DC to 15 MHz Count Frequency * Byte Multiplexer * DC to 1 MHz Scan Frequency * +4.75V to +5.25V Operation (VDD-VSS) * Three-State Data Outputs, Bus and TTL Compatible * Inputs TTL and CMOS Compatible * Unique Cascade Feature Allows Multiplexing of Successive Bytes of Data in Sequence in Multiple Counter Systems * Low Power Dissipation * LS7060, LS7062 (DIP); LS7060-S, LS7062-S (SOIC) See Figures 1 and 2 DESCRIPTION: The LS7060/LS7062 is a monolithic, ion implanted MOS Silicon Gate, 32 bit/dual 16 bit up counter. The IC includes latches, multiplexer, eight three-state binary data output drivers and output cascading logic. DESCRIPTION OF OPERATION: 32 (16) BIT BINARY UP COUNTER - LS7060 (LS7062) The 32(16) bit static ripple through counter increments on the negative edge of the input count pulse. Maximum ripple time is 4s (2s) - transition count of 32(16) ones to 32(16) zeros. Guaranteed count frequency is DC to 15MHz. See Figure 9A(9B) for Block Diagram. COUNT, ALT COUNT (LS7060) Input count pulses to the 32 bit counter may be applied through either of these two inputs. The ALT COUNT input circuitry contains a Schmitt trigger network which allows proper counting with "infinitely" long clock edges. A high applied to either of these two inputs inhibits counting. COUNT A, ALT COUNT A (LS7062) Input count pulses to the first 16 bit counter may be applied through either of these two inputs. The ALT COUNT A input circuitry contains a Schmitt trigger network which allows proper counting with "infinitely" long clock edges. A high applied to either of these two inputs inhibits counting. RESET All 32 counter bits are reset to zero when RESET is brought low for a minimum of 1s. RESET must be high for a minimum of 300ns before next valid count can be recorded. TEST COUNT (LS7060) Count pulses may be applied to the last 16 bits of the binary counter through this input, as long as Bit 16 of the counter is a low. The counter advances on the negative transition of these pulses. This input is intended to be used for test purposes. 7060/62-071698-1 July 1998 PIN ASSIGNMENT - TOP VIEW 18 V DD (+V) 17 B4 OUT 16 B5 OUT 15 B6 OUT COUNT ALT COUNT B3 OUT B2 OUT B1 OUT B0 OUT RESET CASCADE EN OUT LSI 1 2 3 4 5 6 7 8 9 LS7060 14 B7 OUT 13 TEST COUNT 12 SCAN RESET/LOAD 11 ENABLE 10 SCAN V SS (-V) FIGURE 1 PIN ASSIGNMENT - TOP VIEW COUNT A ALT COUNT A B3 OUT B2 OUT B1 OUT B0 OUT RESET CASCADE EN OUT V SS (-) 1 2 3 4 5 6 7 8 9 18 17 16 15 V DD (+V) B4 OUT B5 OUT COUNT B (LS7062) Count pulses may be applied to the last 16 bits of the binary counter through this input. The counter advances on the negative transition of these pulses. LATCHES - LS7060 (LS7062) 32 bits of latch are provided for storage of counter data. All latches are loaded when the LOAD input is brought low for a minimum of 1s and kept low until a minimum of 4s (2s) has elapsed from previous negative edge of count pulse (ripple time). Storage of valid data occurs when LOAD is brought high for a minimum of 250ns before next negative edge of count pulse or RESET. LSI B6 OUT B7 OUT COUNT B SCAN RESET/LOAD ENABLE SCAN LS7062 14 13 12 11 10 FIGURE 2 SCAN COUNTER AND DECODER The scan counter is reset to the least significant byte position (State 1) when SCAN RESET input is brought low for a minimum of 1s. The scan counter is enabled for counting as long as the ENABLE input is held low. The counter advances to the next significant byte position on each negative transition of the SCAN pulse. When the scan counter advances to State 5 it disables the Output Drivers and stops in that state until SCAN RESET is again brought low. SCAN When the scan counter is enabled, each negative transition of this input advances the scan counter to its next state. When SCAN is low the Data Outputs are disabled. When SCAN is brought high the Data Outputs are enabled and present the latched counter data corresponding to the present state of the scan counter. Therefore, in microprocessor applications, the Data Output Bus may be utilized for other activities while new data is propagating to the outputs. This positive SCAN pulse can be viewed as a "Place the next byte on my bus" instruction from the microprocessor. Minimum positive and negative pulse widths of 500ns for the SCAN signal are required for scan counter operation. SCAN RESET/LOAD When this input is brought low for a minimum of 1s, the scan counter is reset to State 1, the least significant byte position, and the latches are simultaneously loaded with new count information. ENABLE When this input is high, the scan counter and the Data Outputs are disabled. When ENABLE is low, the scan counter and Data Outputs are enabled for normal operation. Transition of this input should only be made while the SCAN input is in a low state in order to prevent false clocking of the scan counter. CASCADE ENABLE This output is normally high. It transitions low and stays low when the scan counter advances to State 5. In a multiple counter system this output is connected to the ENABLE input of the next counter in the cascade string. The SCAN input and SCAN RESET/LOAD input are carried to all the counters in the "Cascade". Counter 1 then presents its bytes of data to the Output Bus on each positive transition of the SCAN pulse as previously discussed. When State 5 of Counter 1 is achieved, Counter 2 presents its data to the Output Bus. This sequence continues until all counters in the cascade have been addressed. See Figure 5 for an illustration of a 3 device cascade design. This output is TTL and CMOS compatible. THREE-STATE DATA OUTPUT DRIVERS The eight Data Output Drivers are disabled when either ENABLE input is high, the scan counter is in State 5, or the SCAN input is low. The Output Drivers are TTL and Bus compatible. The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. ABSOLUTE MAXIMUM RATINGS: PARAMETER StorageTemperature Operating Temperature Voltage (any pin to VSS) SYMBOL TSTG TA VIN VALUE -55 to +150 0 to +70 +10 to -0.3 UNIT C C V DC ELECTRICAL CHARACTERISTICS: (VDD = +5V 5%, VSS = 0V, TA = 0C to + 70C unless otherwise noted.) PARAMETER Power Supply Current Input High Voltage Input Low Voltage Output High Voltage CASCADE ENABLE B0 - B7 Output Low Voltage CASCADE ENABLE B0 - B7 Output Source Current B0 - B7 Outputs Output Sink Current B0 - B7 Outputs Output Leakage Current B0 - B7 (Off State) Input Capacitance Output Capacitance Input Leakage Current ENABLE, RESET, SCAN SYMBOL IDD VIH VIL Min +3.5 0 MAX 15 VDD +0.6 UNIT mA V V CONDITIONS At Maximum Operating Frequency VDD = Max, Outputs No Load - VOH VOL VDD-0.2 +2.4 +2.4 +2.0 - Isource Isink IOL CIN COUT ILI 3.0 4.8 7.3 5.7 4.0 2.2 - +0.2 +0.4 +0.4 1 6 12 1 V V V V V V V mA mA mA mA mA mA A pF pF A IO = 0, VDD = Min IO = -100A, VDD = Min IO = -260A, VDD = Min IO = 750A, VDD = Min IO = 0, VDD = Min IO = 1.6mA, VDD = Min IO = 1.6mA, VDD = Min VO = +1.2V, VDD = Min VO = +0.8V, VDD = Min VO = +0.4V, VDD = Min VO = +1.2V, VDD = Min VO = +0.8V, VDD = Min VO = +0.4V, VDD = Min VO = +.4V to +2.4V,VDD = Min TA = 25C, f = 1MHz TA = 25C, f = 1MHz VDD = Max 7060/62-071698-2 INPUT CURRENT *SCAN RESET/LOAD **All Count inputs IIH IIL IIH IIL - -2.5 -5 5 1 A A A A VDD = Max, VIH = +3.5 VDD = Max, VIL = 0 VDD = Max, VIH = +3.5 VDD = Max, VIL = 0 *Input has internal pull-up resistor to VDD ** Inputs have internal pull-down resistor to VSS DYNAMIC ELECTRICAL CHARACTERISTICS: (VDD = +5V 5%, VSS = 0V, TA = 0C to +70C unless otherwise noted.) PARAMETER Count Frequency (All Count inputs) Count Pulse Width (All Count Inputs) Count Rise & Fall time (Pins 1, 13) Count Ripple Time (Pins 1, 2 - LS7062) Count Ripple Time (Pin 13 - LS7060) (Pins 1,2,13 - LS7062) Reset Pulse Width (All Counter Stages Fully Reset) RESET Removal Time (Reset Removed From All Counter Stages) SCAN Frequency SCAN Pulse Wildth SCAN RESET/LOAD Pulse Width (All latches loaded and Scan Counter Reset to Least Significant Byte) SCAN RESET/LOAD Removal Time (Reset Removed from Scan Counter; Load Command Removed From Latches) Output Disable Delay Time (B0 - B7) Output ENABLE Delay Time (B0 - B7) SYMBOL fc tCPW MIN DC 30 MAX 15 UNIT MHz ns CONDITIONS Measured at 50% point, Max tr, tf = 10ns - tr, tf - 30 s tCR - 4 s Transition from 32 ones to 32 zeros from negative edge of count pulse Transition of 16 bits from all ones to all zeros from negative edge of count pulse Measured at 50% point Max tr, tf = 200ns tCR - 2 s tRPW 500 - ns tRR - 250 ns Measured from RESET signal at VIH fSC tSCPW tRSCPW 500 1 1 - MHz ns s Measured at 50% point Max tr, tf = 100ns Measured at 50% point Max tr, tf = 200ns tRSCR - 250 ns Measured from SCAN RESET/ LOAD at VIH tDOD - 200 ns tDOE - 200 ns Output Delay Time CASCADE ENABLE tDCE - 300 ns Transition to Output High Impedance State Measured From Scan at VIL or ENABLE at VIH Transition to Valid On State Measured from Scan at VIH and ENABLE at VIL; Delay to Valid Data Levels for COL =10pF and one TTL Load or Valid Data Currents for High Capacitance Loads Negative Transition from Scan at VIL and ST5 of Scan Counter or Positive Transition From SCAN RESET/LOAD at VIL to Valid Data Levels for COL = 10pF and one TTL Load 7060/62-071398-3 tRSCPW SCAN RESET ENABLE tRSCR SCAN tSCPW tSCPW ST1 (int.) ST2 (int.) ST3 (int.) ST4 (int.) ST5 (int.) ENABLE (int.) tDCE tDCE tDOE valid LSB valid LSB+1 tDOD valid LSB +2 valid MSB CASCADE ENABLE DATA OUTPUTS FIGURE 3. SCAN COUNTER & DECODER OUTPUTS TIMING DIAGRAM tRPW RESET tRPW tRR + tCPW COUNT tRSCR tRR+tCPW LOAD tCPW tCR tCPW tRSCPW FIGURE 4. COUNTER TIMING DIAGRAM OUTPUT DATA BUS CE EN SC RESET SC A CE EN SC RESET SC B CE EN SC RESET SC C END OF SCAN ENABLE SCAN RESET SCAN FIGURE 5. 7060/62-071098-4 ILLUSTRATION OF A 3 DEVICE CASCADE SCAN RESET ENABLE SCAN CASCADE ENABLE A CASCADE ENABLE B CASCADE ENABLE C (END OF SCAN) DATA BYTE ON BUS PACKAGE 1 2 3 A 4 5 1 2 3 B 4 5 1 2 3 C 4 5 FIGURE 6. TIMING DIAGRAM FOR THE 3 DRIVER CASCADE METHOD 1 METHOD 2 INHIBIT INHIBIT S R COUNT PULSES (Same as input to Alt Count) Q TO COUNT INPUT D PR Q TO COUNT INPUT C COUNT PULSES (Same as input to Alt Count) FIGURE 7. SYNCHRONIZING INHIBIT WITH COUNT PULSES FOR LS7060 INHIBIT COUNT PULSES (Same as input to ALT COUNT A) D C Q TO COUNT A COUNT PULSES INHIBIT Q C* (*Reference LS7062 Block Diagram, Figure 9B) NOTE: Count A may only change during positive portion of Count Pulses (Alt Count A) when Count A is used as an inhibit. FIGURE 8. SYNCHRONIZING INHIBIT WITH COUNT PULSES FOR COUNTER A FOR LS7062 7060/62-071398-5 FIGURE 9A. LS7060 BLOCK DIAGRAM CASCADE ENABLE 8 LSB DATA OUT MSB B0 B1 B2 B3 B4 B5 B6 B7 VDD VSS 18 9 +V -V 5 STATE STATIC SCAN COUNTER AND CSC DECODER (STOPS IN STATE 5 UNTIL SCAN RESET RSC CAUSES RESET TO STATE ONE) ST1 ST2 ST3 ST4 ST5 ENABLE 65 4 3 17 16 15 14 ENABLE SCAN SCAN RESET/LOAD 11 10 12 EN THREE STATE OUTPUT DRIVERS 8 BITS 8 BIT MUX BUS G MUX GATE G MUX GATE G MUX GATE G MUX GATE LOAD 8 BIT LATCH LOAD 8 BIT LATCH LOAD 8 BIT LATCH LOAD 8 BIT LATCH B0 COUNT 1 B7 8 BIT BINARY COUNTER B0 C R B7 8 BIT BINARY COUNTER B0 C R B7 8 BIT BINARY COUNTER C B0 B7 8 BIT BINARY COUNTER C R R 2 ALT COUNT 13 7 RESET TEST COUNT 7060/62-071798-6 FIGURE 9B. LS7062 BLOCK DIAGRAM CASCADE ENABLE 8 DATA OUT LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 VDD V SS 18 9 +V -V 11 10 12 6 5 4 3 17 16 15 14 ENABLE SCAN SCAN RESET/LOAD 5 STATE STATIC SCAN COUNTER AND CSC DECODER (STOPS IN STATE 5 UNTIL SCAN RESET RSC CAUSES RESET TO STATE ONE) ST1 ST2 ST3 ST4 ST5 ENABLE EN THREE STATE OUTPUT DRIVERS 8 BITS 8 BIT MUX BUS MUX GATE MUX GATE MUX GATE MUX GATE G G G G LOAD 8 BIT LATCH LOAD 8 BIT LATCH LOAD 8 BIT LATCH LOAD 8 BIT LATCH B0 COUNT A 1 C R B7 8 BIT BINARY COUNTER B0 C R B7 8 BIT BINARY COUNTER B0 C R B7 8 BIT BINARY COUNTER B0 C R B7 8 BIT BINARY COUNTER 2 ALT COUNT 13 7 COUNT B RESET 7060/62-071798-7 |
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